module rx_bps_clk_gen #(
	parameter CLK_FREQ  = 50_000_000 ,//50MHZ
	parameter BAUD_RATE = 9600
	)(
	input wire 		clk ,
	input wire		rst_n ,
	input wire 		rx_start ,
	input wire 	    rx_done  ,
	output logic 	sample_clk //接收采样时钟
);
	//采样时钟为baud rate的9倍，为了可以正确采集到信号而设置.
	localparam SAMPLE_CLK_CNT = CLK_FREQ /( BAUD_RATE * 9 )- 1 ; 
	localparam SAM_CLK_CNT_WD = ($clog2(SAMPLE_CLK_CNT)-1) ;

	logic [SAM_CLK_CNT_WD-1:0] clk_cnt ;
	logic sta ; //current state
	logic n_sta ; //next state


	always_ff @(posedge clk or negedge rst_n) begin : proc_sta
		if(~rst_n) begin
			sta <= 0;
		end else begin
			sta <= n_sta;
		end
	end

	always_comb begin : state_generate
		case(sta) 
			1'b0 : n_sta = rx_start ? 1'b1 : 1'b0 ;
			1'b1 : n_sta = rx_done  ? 1'b0 : 1'b1 ;
			default : begin n_sta = 1'b0 ; end
		endcase // stadcase
	end


	always_ff @(posedge clk or negedge rst_n) begin : proc_clk_cnt
		if(~rst_n) begin
			clk_cnt <= 0;
		end else begin
			if(sta == 1'b0)begin	
				clk_cnt <= 'd0 ;
			end else if(clk_cnt == SAMPLE_CLK_CNT) begin
				clk_cnt <= 'd0 ;
			end else begin
				clk_cnt <= clk_cnt + 1'b1 ;
			end
		end
	end
	//generate the sample clk = 9*baud rate 
	always_ff @(posedge clk or negedge rst_n)begin : proc_sample_clk
		if(~rst_n)begin	
			sample_clk <= 1'b0 ;
		end else begin
			if(clk_cnt == 1'b1) begin
				sample_clk <= 1'b1 ;
			end else begin
				sample_clk <= 1'b0 ;
			end
		end
	end



endmodule : rx_bps_clk_gen